#define INST_RETIRED_ANY   ((0x01 << 8) | 0x00)
#define CPU_CLK_UNHALTED_CORE  ((0x02 << 8) | 0x00)
#define CPU_CLK_UNHALTED_REF_TSC   ((0x03 << 8) | 0x00)
#define LD_BLOCKS_DATA_UNKNOWN ((0x01 << 8) | 0x03)
#define LD_BLOCKS_STORE_FORWARD    ((0x02 << 8) | 0x03)
#define LD_BLOCKS_4K_ALIAS ((0x04 << 8) | 0x03)
#define LD_BLOCKS_UTLB_MISS    ((0x08 << 8) | 0x03)
#define LD_BLOCKS_ALL_BLOCK    ((0x10 << 8) | 0x03)
#define PAGE_WALKS_D_SIDE_CYCLES   ((0x01 << 8) | 0x05)
#define PAGE_WALKS_I_SIDE_CYCLES   ((0x02 << 8) | 0x05)
#define PAGE_WALKS_CYCLES  ((0x03 << 8) | 0x05)
#define UOPS_ISSUED_ANY    ((0x00 << 8) | 0x0E)
#define MISALIGN_MEM_REF_LOAD_PAGE_SPLIT   ((0x02 << 8) | 0x13)
#define MISALIGN_MEM_REF_STORE_PAGE_SPLIT  ((0x04 << 8) | 0x13)
#define LONGEST_LAT_CACHE_MISS ((0x41 << 8) | 0x2E)
#define LONGEST_LAT_CACHE_REFERENCE    ((0x4F << 8) | 0x2E)
#define L2_REJECT_XQ_ALL   ((0x00 << 8) | 0x30)
#define CORE_REJECT_L2Q_ALL    ((0x00 << 8) | 0x31)
#define CPU_CLK_UNHALTED_CORE_P    ((0x00 << 8) | 0x3C)
#define CPU_CLK_UNHALTED_REF   ((0x01 << 8) | 0x3C)
#define DL1_DIRTY_EVICTION ((0x01 << 8) | 0x51)
#define ICACHE_HIT ((0x01 << 8) | 0x80)
#define ICACHE_MISSES  ((0x02 << 8) | 0x80)
#define ICACHE_ACCESSES    ((0x03 << 8) | 0x80)
#define ITLB_MISS  ((0x04 << 8) | 0x81)
#define FETCH_STALL_ALL    ((0x00 << 8) | 0x86)
#define FETCH_STALL_ITLB_FILL_PENDING_CYCLES   ((0x01 << 8) | 0x86)
#define FETCH_STALL_ICACHE_FILL_PENDING_CYCLES ((0x02 << 8) | 0x86)
#define UOPS_NOT_DELIVERED_ANY ((0x00 << 8) | 0x9C)
#define INST_RETIRED_ANY_P ((0x00 << 8) | 0xC0)
#define UOPS_RETIRED_ANY   ((0x00 << 8) | 0xC2)
#define UOPS_RETIRED_MS    ((0x01 << 8) | 0xC2)
#define UOPS_RETIRED_FPDIV ((0x08 << 8) | 0xC2)
#define UOPS_RETIRED_IDIV  ((0x10 << 8) | 0xC2)
#define MACHINE_CLEARS_ALL ((0x00 << 8) | 0xC3)
#define MACHINE_CLEARS_SMC ((0x01 << 8) | 0xC3)
#define MACHINE_CLEARS_MEMORY_ORDERING ((0x02 << 8) | 0xC3)
#define MACHINE_CLEARS_FP_ASSIST   ((0x04 << 8) | 0xC3)
#define MACHINE_CLEARS_DISAMBIGUATION  ((0x08 << 8) | 0xC3)
#define BR_INST_RETIRED_ALL_BRANCHES   ((0x00 << 8) | 0xC4)
#define BR_INST_RETIRED_JCC    ((0x7E << 8) | 0xC4)
#define BR_INST_RETIRED_ALL_TAKEN_BRANCHES ((0x80 << 8) | 0xC4)
#define BR_INST_RETIRED_FAR_BRANCH ((0xBF << 8) | 0xC4)
#define BR_INST_RETIRED_NON_RETURN_IND ((0xEB << 8) | 0xC4)
#define BR_INST_RETIRED_RETURN ((0xF7 << 8) | 0xC4)
#define BR_INST_RETIRED_CALL   ((0xF9 << 8) | 0xC4)
#define BR_INST_RETIRED_IND_CALL   ((0xFB << 8) | 0xC4)
#define BR_INST_RETIRED_REL_CALL   ((0xFD << 8) | 0xC4)
#define BR_INST_RETIRED_TAKEN_JCC  ((0xFE << 8) | 0xC4)
#define BR_MISP_RETIRED_ALL_BRANCHES   ((0x00 << 8) | 0xC5)
#define BR_MISP_RETIRED_JCC    ((0x7E << 8) | 0xC5)
#define BR_MISP_RETIRED_NON_RETURN_IND ((0xEB << 8) | 0xC5)
#define BR_MISP_RETIRED_RETURN ((0xF7 << 8) | 0xC5)
#define BR_MISP_RETIRED_IND_CALL   ((0xFB << 8) | 0xC5)
#define BR_MISP_RETIRED_TAKEN_JCC  ((0xFE << 8) | 0xC5)
#define ISSUE_SLOTS_NOT_CONSUMED_ANY   ((0x00 << 8) | 0xCA)
#define ISSUE_SLOTS_NOT_CONSUMED_RESOURCE_FULL ((0x01 << 8) | 0xCA)
#define ISSUE_SLOTS_NOT_CONSUMED_RECOVERY  ((0x02 << 8) | 0xCA)
#define HW_INTERRUPTS_RECEIVED ((0x01 << 8) | 0xCB)
#define HW_INTERRUPTS_MASKED   ((0x02 << 8) | 0xCB)
#define HW_INTERRUPTS_PENDING_AND_MASKED   ((0x04 << 8) | 0xCB)
#define CYCLES_DIV_BUSY_ALL    ((0x00 << 8) | 0xCD)
#define CYCLES_DIV_BUSY_IDIV   ((0x01 << 8) | 0xCD)
#define CYCLES_DIV_BUSY_FPDIV  ((0x02 << 8) | 0xCD)
#define MEM_UOPS_RETIRED_DTLB_MISS_LOADS   ((0x11 << 8) | 0xD0)
#define MEM_UOPS_RETIRED_DTLB_MISS_STORES  ((0x12 << 8) | 0xD0)
#define MEM_UOPS_RETIRED_DTLB_MISS ((0x13 << 8) | 0xD0)
#define MEM_UOPS_RETIRED_LOCK_LOADS    ((0x21 << 8) | 0xD0)
#define MEM_UOPS_RETIRED_SPLIT_LOADS   ((0x41 << 8) | 0xD0)
#define MEM_UOPS_RETIRED_SPLIT_STORES  ((0x42 << 8) | 0xD0)
#define MEM_UOPS_RETIRED_SPLIT ((0x43 << 8) | 0xD0)
#define MEM_UOPS_RETIRED_ALL_LOADS ((0x81 << 8) | 0xD0)
#define MEM_UOPS_RETIRED_ALL_STORES    ((0x82 << 8) | 0xD0)
#define MEM_UOPS_RETIRED_ALL   ((0x83 << 8) | 0xD0)
#define MEM_LOAD_UOPS_RETIRED_L1_HIT   ((0x01 << 8) | 0xD1)
#define MEM_LOAD_UOPS_RETIRED_L2_HIT   ((0x02 << 8) | 0xD1)
#define MEM_LOAD_UOPS_RETIRED_L1_MISS  ((0x08 << 8) | 0xD1)
#define MEM_LOAD_UOPS_RETIRED_L2_MISS  ((0x10 << 8) | 0xD1)
#define MEM_LOAD_UOPS_RETIRED_HITM ((0x20 << 8) | 0xD1)
#define MEM_LOAD_UOPS_RETIRED_WCB_HIT  ((0x40 << 8) | 0xD1)
#define MEM_LOAD_UOPS_RETIRED_DRAM_HIT ((0x80 << 8) | 0xD1)
#define BACLEARS_ALL   ((0x01 << 8) | 0xE6)
#define BACLEARS_RETURN    ((0x08 << 8) | 0xE6)
#define BACLEARS_COND  ((0x10 << 8) | 0xE6)
#define MS_DECODED_MS_ENTRY    ((0x01 << 8) | 0xE7)
#define DECODE_RESTRICTION_PREDECODE_WRONG ((0x01 << 8) | 0xE9)
